Computer designers are always searching for faster memory devices that will allow them to design faster computers. Typically, a computer's operating speed depends upon the time required to transfer, i.e., read or write, data between a processor and a memory circuit, such as a dynamic random access memory (DRAM). Such a memory circuit usually includes a large number of memory cells that are arranged in rows and columns. These cells store both data for the processor to operate on and the results of such operations. Therefore, the more quickly the processor can access the data within these memory cells, the more quickly it can perform a calculation or execute a program that uses this data.
Typically, to read data from a memory device, a computer processor or other addressing circuit generates row and column addresses on an address bus and row and column address strobes (RAS and CAS respectively) on respective strobe lines. The data that the memory device provides to the processor, i.e., the data read by the processor, are stored in the unique memory cells that are part of both the selected rows and the corresponding selected columns. Such a memory device can often operate in at least four read modes or cycles: nibble, burst extended data out (EDO), page mode, and conventional read. The term "extended data out" indicates that the memory device can place valid data on the DATA bus even when CAS is in an inactive state.
Referring to the timing diagram of FIG. 1, to initiate a nibble read cycle, the processor (not shown) generates a row address on the address bus. Next, the processor transitions RAS from a first inactive state or logic level to a second active state or logic level so that the memory device stores or latches the row address. The processor then generates a column address on the address bus and transitions CAS from an inactive to an active level. In this embodiment, the active logic level is logic 0 and the inactive logic level is logic 1 for both RAS and CAS. (The bar over the signal name indicates the signal is active low.) Other embodiments, however, may use different logic levels for the active and inactive levels. Furthermore, a transition from logic 1 to logic 0 is referred to as a falling edge, and a transition from a logic 0 to logic 1 is a rising edge.
In response to the CAS transition, the memory device latches the column address and loads into output buffers the data stored in the memory cells located in the addressed row at the column address and at a predetermined number of sequential column addresses in the same row. For example, as shown, if the addressed row and column are at addresses ROW+0 and COL+0 respectively, the memory device loads into the output buffers the contents of the memory cells located in ROW+0 at COL+0, COL+1, and COL+3. Also in response to the CAS transition, the output buffer containing the data from column! COL 0 drives, i.e., places, its contents onto the DATA bus. In response to subsequent falling edges of CAS, the remaining output buffers are enabled such that they pace their contents on the DATA bus. After it has read the addressed data, the processor transitions both CAS and RAS to inactive levels to disable the memory from placing data on the DATA bus. Although in this embodiment the memory device is programmed to access the memory cells in four sequential columns, the memory device may access any number, i.e., nibble, of cells in any column position.
Still referring to FIG. 1, and, for example purposes, using a 66 MHz clock, i.e., a clock having a period of 15 nanoseconds and edges labeled 0-12, the nibble read cycle takes between 12-13 clock cycles, i.e., 180-195 nanoseconds. The t.sub.RAC time, which is the duration between the falling edge of RAS and the time when the memory device first places valid data onto the DATA bus, is between 50 and 60 nanoseconds, and the time t.sub.RP, which is the time that RAS must be at an inactive logic level before the start of the next cycle, is approximately 30-40 nanoseconds. Also as shown, the data on the DATA bus is valid only when CAS is at an active level, taking into account the propagation delays within the memory device. Furthermore, after the rising edge of RAS, if CAS goes to a logic 1, no more data can be read from or written to the memory device until RAS transitions low to begin the next cycle.
FIG. 2 is a timing diagram that illustrates a burst EDO (BEDO) read cycle. Initially, the processor drives a row address ROW+0 onto the address bus and the memory latches the row address in response to the falling edge of RAS . The processor then drives a base column address onto the address bus, and in response to the first falling edge of CAS, the memory latches the base column address. FIG. 2 shows the base column address as an initial column address plus a 0 index, i.e., COL+0. In response to the next falling edge of CAS, the memory updates the index, and places the data from the 0 index column COL+0 onto the DATA bus. In the illustrated embodiment, the memory increments the index by one to update it, although other embodiments may use other algorithms to update the index to point to any column in the addressed row. In response to each subsequent falling edge of CAS, the memory updates the index and drives the data from the previously indexed column--COL+1, COL+2, and COL+3 sequentially--onto the DATA bus. This updating and driving sequence continues until the index reaches a predetermined value, which equals three in this embodiment. After the index reaches the predetermined value, the processor places on the address bus the next column address COL+4, which in this embodiment is the sum of the base column address COL+0 and the predetermined index value (3) plus 1. In response to the next falling edge of CAS after the index reaches the predetermined value, the memory latches this new column address COL+4 and places on the DATA bus the data from the previously indexed column COL+3, which in this embodiment is the column located at the sum of the base column address COL+0 and the predetermined index value (3). This whole cycle may then repeat itself any number of times, up until the processor has accessed every column (COL+0, COL+1, COL+2, COL+3, COL+4, COL+5 . . . ) in the addressed row. Thus, during a BEDO read cycle, the memory device can output data from a large number of columns in the same row without requiring the processor to periodically re-address the row. Although not shown, at the end of the BEDO cycle, the processor transitions RAS to a logic 1 for at least time t.sub.RP before transitioning it to a logic 0 to begin another cycle.
Still referring to FIG. 2, and, for example purposes, using a 66 MHz clock frequency having edges labeled 0-9, the read cycle requires a time that is approximately equal to the sum of the number of columns accessed times the clock period (15 ns), t.sub.RAC, and t.sub.RP (not shown). In this example, t.sub.RAC is approximately 60-75 nanoseconds, and t.sub.RP is approximately 30-40 nanoseconds. Also, after the rising edge of RAS, the read cycle ends if CAS is a logic 1, or, if CAS is a logic 0, when CAS transitions to a logic 1. Once the read cycle ends, the memory device cannot place valid data on or retrieve valid data from the DATA bus until the next read or write cycle.
FIG. 3 is a timing diagram of a page mode EDO read cycle. Initially, the processor drives the row address onto the address bus and the memory latches the row address in response to the falling edge of RAS. The processor then drives a column address onto the address bus. In response to the first falling edge of CAS, the memory latches the column address, and places on the DATA bus the data from the memory cell located at the column (COL+0) and row (ROW+0) addresses. The processor then drives a second column address onto the address bus, here COL+1. In response to the next falling edge of CAS, the memory latches this column address COL+1 and places on the DATA bus the data from the memory cell located at the second column address (COL+1) and the row address (ROW+0). As shown, such a sequence can continue for any number of CAS cycles up until every column (COL+2, COL+3, . . . COL+(N-1), COL+N . . . ) in the addressed row has been read. The processor then transitions RAS and CAS high to end the read cycle. The page mode EDO is similar to both the nibble and BEDO read cycles in that multiple columns can be read from a single row that has been addressed only once. Unlike the nibble and the BEDO cycles, in which the memory generates most of the column addresses internally, when operating in the page mode EDO, the processor must supply each column address to the memory.
Still referring to FIG. 3, and using, for example purposes, a 66 MHz clock having edges labeled 0-9, k, and k+1, the page mode EDO read cycle requires a time that is approximately equal to the sum of t.sub.RAC, the number of CAS cycles times four clock periods, and t.sub.RP. In this example, t.sub.RAC is approximately 50-60 nanoseconds, and t.sub.RP is approximately 30-40 nanoseconds. Also, DATA bus after the rising edge of RAS, the page mode EDO cycle ends if CAS is inactive logic 1, or in response to the next rising edge of CAS.
FIG. 4 is a timing diagram of a normal-mode read cycle. Initially, the processor drives the row address ROW+0 onto the address bus and the memory latches the row address in response to the falling edge of RAS. The processor then drives a column address (COL+0) onto the address bus. In response to the falling edge of CAS, the memory latches the column address (COL+0), and places on the DATA bus the data from the memory cell located at the column and row addresses. The processor then transitions CAS to a logic 1 to disable the memory from outputting data. A predetermined time later, the processor transitions RAS to a logic 1 for at least the predetermined time t.sub.RP before transitioning RAS to a logic 0 to begin the next cycle, which, for example, accesses ROW+1. Thus, the normal-mode read mode is typically used to address a single column in a row.
Still referring to FIG. 4, and using for example purposes a 66 MHz clock having edges labeled 0-9, the normal-mode read cycle requires approximately 9 clock cycles. In this example, t.sub.RAC is approximately 50-60 nanoseconds, and t.sub.RP is approximately 30-40 nanoseconds. Also, DATA bus after the rising edge of RAS, the convention read cycle ends if CAS is at an inactive logic 1, or in response to the next rising edge of CAS.
Attempts to decrease the cycle times for the nibble, BEDO, page EDO, normal-mode, and other read modes have focused on increasing the frequency of the system clock. With today's integrated circuit technology, however, the speed of the clock is limited by the propagation and other delay times associated with memory devices.